A NAND-type flash memory is a well-known semiconductor memory device that can store data in a nonvolatile fashion with high storage capacity. A cell array of NAND-type flash memory is formed by arranging NAND cell units in which several memory cells are connected in series. Word and bit lines are used to read and write data to specific memory cells. Word lines connect memory cells in different cell units and bit lines each connect to a different cell unit.
A potential problem with NAND-type flash memory is that a parasitic capacitance between adjacent or near-by word lines increases as device feature sizes decrease as a result of device miniaturization. As more memory cells and, therefore, word lines are included in smaller spaces there are increasing problems with parasitic capacitance between word lines, which may adversely affect device performance.
Due to parasitic capacitance, when a desired (predetermined) voltage for reading or writing data is supplied to selected word lines, a voltage overshoot is sometimes caused in the selected word lines by capacitive coupling with adjacent word lines. If the overshoot is large, device response time is delayed until the desired voltage is actually obtained. Delayed response times can cause poor device performance. This capacitive coupling phenomenon is especially distinct in three-dimensional NAND-type flash memory arrays.